This invention relates generally to dual port random access memory cells implemented in CMOS technology and more particularly, it relates to a CMOS dual port memory cell which provides for read-only isolation but yet has a higher layout packing density than has been traditionally available.
As is generally known in the art, dual port random access to a memory cell means that the random access memory cell has two independent data and address lines which are arrayed and interconnected for accessing the memory cell. This duality allows operations to be accomplished simultaneously or in any desired timing relationship and independently of each other (i.e., asynchronously at different data rates). One use of such dual port random access memory (RAM) cells is that it permits data to be passed between asynchronous microprocessors without establishing a handshake model which slows down the faster processor. With such dual port RAM cells, the faster processor can store, via a first "A" port, data into the dual port RAM cells, where such data can later be accessed through a second "B" port by the slower processor operated at a slower rate.
A prior art example of a CMOS dual port random access memory cell 10 is illustrated in FIG. 1. The memory cell 10 is formed of two CMOS cross-coupled inverters 12 and 14 (each consisting of a P-channel transistor and an N-channel transistor) defining a flip-flop core memory and is coupled to two independent sets of different data bit lines. The first set of bit lines BLA and BLA defining a first "A" port are coupled to the core memory via two N-channel pass transistors 16 and 18. The second set of bit lines BLB and BLB defining a second "B" port are also coupled to the core memory via two N-channel pass transistors 20 and 22. The entire memory cell 10 thus consists of eight transistors and is sometimes referred to as an 8-transistor dual port RAM cell. In order to provide a read/write access capability on port A, a word line ROW SELA assumes a high or logic "1" level. In order to provide a read/write access capability on port B, a word line ROW SELB assumes a high or logic "1 " level.
The main problem encountered by this prior art memory cell 10 of FIG. 1 is the "read-disturb" phenomenon wherein when there is a read operation performed the core memory can be disturbed and thus results in a memory loss. In this memory cell 10, this problem is increased due to the fact of the two possible read ports. In order to design around this problem, the four N-channel pass transistors 16-22 are required to be reduced in size so as to provide a lower impedance path from the core memory cell inverters 12 and 14 to the corresponding bit line pairs. However, the sizing down of these pass transistors cause the circuit to lose performance in the read-access mode. While there have been attempts made in the prior art to regain this performance lost by employing clocking techniques, this suffers from the disadvantages of requiring additional precharge/evaluate circuitry as well as a differential sense amplifier which increases the clip area and production costs.
Further, there are many dual port memory systems designed today that do not require a true dual port functionality of read/write access capability at each port. Frequently, each port may have a dedicated function such as "read-only" or "write-only" operation. A prior art example of a CMOS dual port RAM cell 10a with port B designated as a "read-only" port is depicted in FIG. 2. As can be seen, this memory cell 10a has nine transistors which is one more than the conventional 8-transistor dual port RAM cell of FIG. 1. The memory cell 10a has advantages in that the two cross-coupled inverters 24 and 26 can be sized down since the read-access of the port B will not disturb the core memory.
In particular, the memory cell 10a is formed of two CMOS cross-coupled inverters 24 and 26 (each consisting of a P-channel transistor and an N-channel transistor) defining a flip-flop core memory and is coupled to first and second complementary write-only data bit lines BLA and BLA. The first and second write-only data bit lines define a first "C" port and is coupled to the core memory via two N-channel pass transistors 28 and 30. A read-only data bit line BLB defining a second "D" port is coupled to the core memory via an isolation inverter 32 and a third pass transistor 34. This memory cell 10a consists of nine transistors, which is one more than the conventional 8-transistor dual port RAM cell. In order to provide the "write-only" access capability on the port C, a word line ROW SELA defining a write-only address line assumes a high or logic "1" level. In order to provide the "read-only" access capability on the port D, a word line ROW SELB defining a read-only address line assumes a high or logic "1" level.
The disadvantage suffered by the memory cell 10a of FIG. 2 is that the physical layout is not as optimized as the circuit of FIG. 1. By comparing the two different memory cells of FIGS. 1 and 2, it will be noted that there are three interconnect well crossings in FIG. 2 as opposed to the two well crossings in FIG. 1. A well crossing is required every time an interconnect is used to connect an N-channel device to a P-channel device. As is generally known to those skilled in the art, the number of well crossings used is an important factor in determining the overall core cell area.
As the storage capacity of semiconductor memory devices become greater and greater in recent developments, one of the techniques of increasing the integration density of the integrated circuit chip without increasing chip area is through the reduction of the number of well crossings during the physical layout of the memory cell. Accordingly, it would therefore be desirable to provide a CMOS dual port memory cell which has an improved layout packing density. The CMOS dual port memory cell of the present invention represents a second improvement over the prior art memory cells of FIGS. 1 and 2.